The present invention concerns the cell structure of BiCMOS, and more particularly a method of fabricating BiCMOS field effect transistors (FETs) used in a very large scale integrated circuits (VLSI).
In a conventional BiCMOS type field effect transistor, a Bipolar device is isolated from a metal oxide semiconductor device in a silicon substrate, and therefore a metal line must be used to electrically connect the two devices.
Moreover, the current drive capability that is the advantage of the BiCMOS device is usually obtained by connecting the drain of the NMOS to the collector of the NPN bipolar device, and the source of the NMOS to the base of the NPN bipolar device. Likewise, the drain of the PMOS is connected to the base of the NPN bipolar device, and the source of the PMOS to the collector of the NPN bipolar device.
Such NPN-NMOS and NPN-PMOS pairs each function as a complementary device, and if being connected like CMOS, it complementarily operates used as a logic circuit without static power consumption.
If the bipolar device and the MOS device are separately fabricated in a conventional manner in order to construct such a circuit, undesirable external connections are needed so that the area for connecting metal lines is much consumed throughout a chip. There is disclosed a method of fabricating a BiCMOS device of such a construction in U.S. Pat. No. 4,868,135 issued on Sep. 19, 1989.
In this U.S. patent, there is used only a diffusion layer for connecting a P-type FET and an NPN transistor, or N-type FET and a PNP transistor. Namely, the P-type FET is connected to the NPN transistor by using only a P.sup.+ diffusion layer, and the N-type FET to the PNP by using only a N.sup.+ diffusion layer, and therefore the electrical characteristics of the devices are degraded.